Methods of fabricating contact interfaces

ABSTRACT

A contact used in testing semiconductor devices components includes a protrusion that is configured to be received by a semiconductor device component and a silicide layer, or interface, over at least a portion of the protrusion. The silicide layer may be formed with a barrier layer, such as titanium nitride, and an underlying thin dielectric layer between a silicon-containing substrate and a silicidable material or a silicide. The barrier layer prevents the formation of electrical passages, formed by the silicidable material or a silicide thereof, within imperfections or voids through the thin dielectric layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/620,003,filed Jul. 14, 2003, pending, which is a continuation of applicationSer. No. 10/174,164, filed Jun. 17, 2002, now U.S. Pat. No. 6,599,832,issued Jul. 29, 2003, which is a divisional of application Ser. No.09/795,882, filed Feb. 28, 2001, now U.S. Pat. No. 6,410,420, issuedJun. 25, 2002, which is a continuation of application Ser. No.09/136,384, filed Aug. 19, 1998, now U.S. Pat. No. 6,235,630, issued May22, 2001.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to contact interfaces on the surface ofsemiconductor substrates and methods of forming the same. Moreparticularly, the present invention relates to forming silicideinterfaces for use with thin film devices and backend integrated circuit(“IC”) testing devices.

2. Background of Related Art

In the processing of integrated circuits, electrical contact must bemade to isolated active-device regions formed within a semiconductorsubstrate, such as a silicon wafer. Such active-device regions mayinclude p-type and n-type source and drain regions used in theproduction of NMOS, PMOS, and CMOS structures for production of DRAMchips and the like. The active-device regions are connected byconductive paths or lines which are fabricated above an insulative ordielectric material covering a surface of the semiconductor substrate.To provide electrical connection between the conductive path and theactive-device regions, openings in the insulative material are generallyprovided to enable a conductive material to contact the desired regions,thereby forming a “contact.” The openings in the insulative material aretypically referred to as “contact openings.”

Higher performance, lower cost, increased miniaturization of components,and greater packaging density of integrated circuits are goals of thecomputer industry. However, as components become smaller and smaller,tolerances for all semiconductor structures (such as circuitry traces,contacts, dielectric thickness, and the like) become more and morestringent. In fact, each new generation of semiconductor devicetechnology has seen a reduction in contact size of, on average, about0.7 times. Further, the reduction in size of integrated circuits alsoresults in a reduction in the height of the integrated circuits.

Of course, the reduction in contact size (i.e., diameter) has resultedin a greatly reduced area of contact between the active-device regionsand the conductive material. Regardless of the conductive material usedto fill these small contact openings to form the contacts (such astungsten or aluminum), the interface between the conductive material andactive-device region must have a low resistance.

Various methods have been employed to reduce the contact resistance atthe interface between the conductive material and active-device region.One such method includes the formation of a metal silicide contactinterface atop the active-device region within the contact opening priorto the application of the conductive material into the contact opening.A common metal silicide material formed is cobalt silicide (CoSi_(x),wherein x is predominately equal to 2) generated from a deposited layerof cobalt. Cobalt silicide is preferred for shallow junctions of thinfilm structures because it forms very smooth, fine grained silicide, andwill not form tightly bonded compounds with arsenic or boron atoms usedin the doping of shallow junctions.

FIGS. 27-31 illustrate a common method of forming a cobalt silicidelayer on an active-device region of a thin film semiconductor device.FIG. 27 illustrates an intermediate structure 400 comprising asemiconductor substrate 402 with a polysilicon layer 404 thereon,wherein the polysilicon layer 404 has at least one active-device region406 formed therein with a thin dielectric layer 408, such as tetraethylorthosilicate—TEOS, disposed thereover. The dielectric layer 408 must beas thin as possible to reduce the height of the thin film semiconductordevice. A contact opening 412 is formed, by any known technique, such aspatterning and etching, in the dielectric layer 408 to expose a portionof the active-device region 406, as shown in FIG. 28. A thin layer ofcobalt 414 is applied over the dielectric layer 408 and the exposedportion of the active-device region 406, as shown in FIG. 29. A hightemperature anneal step is conducted in an inert atmosphere to react thethin cobalt layer 414 with the active-device region 406 in contacttherewith which forms a cobalt silicide layer 416, as shown in FIG. 30.However, dielectric materials, such as TEOS—tetraethyl orthosilicate,BPSG—borophosphosilicate glass, PSG—phosphosilicate glass, andBSG—borosilicate glass, and the like, are generally porous. Thus, thethin dielectric layer 408 has imperfections or voids which form passagesthrough the thin dielectric layer 408. Therefore, when thehigh-temperature anneal is conducted, cobalt silicide also forms inthese passages. The cobalt silicide structures in the passages arereferred to as patches 418, as also shown in FIG. 30. When thenonreacted cobalt layer 414 is removed to result in a final structure422 with a cobalt silicide layer 416 formed therein, as shown in FIG.31, the patches 418 also form conductive paths between the upper surfaceof the thin dielectric layer 408 which can cause shorting and currentleakage on IC backend testing devices which leads to poor repeatabilityand, thus, poor reliability of the data from the testing devices.

Although such voids can be eliminated by forming a thicker dielectriclayer 424, the thicker dielectric layer 424 leads to poor step coverageof the cobalt material 426 in bottom corners 428 of the contact opening412, as shown in FIG. 32. The poor step coverage is caused by a build-upof cobalt material 426 on the upper edges 432 of the contact opening 412which causes shadowing of bottom corners 428 of the contact openings412. The result is little or no cobalt material 426 deposited at thebottom corners 428 of the contact opening 412 and consequently aninefficient silicide contact formed after annealing.

Step coverage can be improved by using filtering techniques, such asphysical collimated deposition and low-pressure long throw techniques,which are used to increase the number of sputtered particles contactingthe bottom of the contact opening. However, such filtering techniquesare costly and the equipment is difficult to clean. Furthermore,filtering techniques also reduce the deposition rate of the cobaltmaterial which reduces product throughput and, in turn, increases thecost of the semiconductor device. Moreover, using a thick dielectriclayer is counter to the goal of reducing semiconductor device size.Finally, a thick dielectric layer eliminates the ability of thestructure to be used as a backend IC probing device since the contactsare too small and too deep in the dielectric material. This is a resultof dielectric material not being scalable. As device geometries getsmaller, the thickness of the dielectric cannot be reduced without thepotential of shorting and/or formation of patches. Thus, contact sizemust be increased to allow probe tips to fit in contacts, which iscounter to the goal of reducing semiconductor device size.

Thus, it can be appreciated that it would be advantageous to develop atechnique and a contact interface which is free from patch formations,while using inexpensive, commercially available, widely practicedsemiconductor device fabrication techniques and equipment withoutrequiring complex processing steps.

SUMMARY OF THE INVENTION

The present invention relates to methods of forming silicide interfacesfor use with thin film devices and backend integrated circuit testingdevices and structures so formed. The present invention is particularlyuseful when a porous dielectric layer is disposed between asilicon-containing substrate and a silicidable material deposited toform a silicide contact in a desired area. As previously discussed,dielectric layers may have imperfections or voids which form passagesthrough the thin dielectric layer. Therefore, when the high-temperatureanneal is conducted to form the silicide contact from the reaction ofthe silicidable material and the silicon-containing substrate, asilicide material may also form in these passages through the dielectricmaterial. Such silicide material extending through these passages cancause shorting and current leakage. The present invention prevents theformation of silicide material through passages in the dielectricmaterial by the application of a barrier layer between the dielectricmaterial and the silicidable material.

In an exemplary method of forming a contact according to the presentinvention, a semiconductor substrate is provided with a polysiliconlayer disposed thereon, wherein at least one active-device region isformed in a polysilicon layer. A thin dielectric layer is deposited orgrown (such as by a thermal oxidation process) over the polysiliconlayer and a layer of barrier material, preferably titanium nitride, isdeposited over the thin dielectric layer.

A mask material is patterned on the barrier material layer and a contactopening is then etched through the barrier material layer and the thindielectric layer, preferably by an anisotropic etch, to expose a portionof the active-device region. Any remaining mask material is removed anda thin layer of silicidable material, such as cobalt, titanium,platinum, or palladium, is deposited over the barrier material layer andinto the contact opening over the exposed portion of the active-deviceregion. A high temperature anneal is conducted to react the thinsilicidable material layer with the active-device region in contacttherewith, which forms a silicide contact. The barrier material preventsthe formation of silicide structures within voids and imperfections inthe thin dielectric layer. The nonreacted silicidable material layer andremaining barrier material layer are then removed.

In an exemplary method of forming a testing contact used in backendtesting of semiconductor devices, a silicon-containing substrate isprovided having at least one contact projection disposed thereon. Afirst dielectric layer is deposited or grown over the substrate and thecontact projection. A layer of polysilicon is then deposited over thefirst dielectric layer. A second dielectric layer is optionallydeposited over the polysilicon layer and a layer of barrier material isdeposited over the optional second dielectric layer, or over thepolysilicon, if the optional second dielectric layer is not used.

A mask material is patterned on the barrier material layer. The barriermaterial layer and the optional second dielectric layer (if used) arethen etched to expose the polysilicon layer over the contact projection,then any remaining mask material is removed. A thin layer of silicidablematerial is deposited over the barrier material layer and onto theexposed contact projection. A high temperature anneal is conducted toreact the thin silicidable material layer with the exposed portion ofthe polysilicon layer over the contact projection which forms a silicidelayer. The nonreacted silicidable material layer and the remainingbarrier material layer are then removed to form the testing contact.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the advantages of this invention can be more readily ascertained fromthe following description of the invention when read in conjunction withthe accompanying drawings in which:

FIGS. 1-8 are cross-sectional views of a method of forming a contactinterface in a thin semiconductor structure according to the presentinvention;

FIG. 9 is a cross-sectional view of CMOS structures within a memoryarray of a DRAM chip formed by a method according to the presentinvention;

FIGS. 10-17 are cross-sectional views of a method of forming a testinginterface according to the present invention;

FIG. 18 is a cross-sectional view of a testing interface according tothe present invention with a chip-under-test disposed therein;

FIGS. 19-26 are cross-sectional views of another method of forming atesting interface according to the present invention;

FIGS. 27-31 are cross-sectional views of a method of forming a contactinterface in a thin semiconductor structure according to a knowntechnique; and

FIG. 32 is a cross-sectional view of the deposition of a metal layer inan opening in a thick dielectric according to a known technique.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1-8 illustrate a method of forming a contact interface of thepresent invention. It should be understood that the illustrations arenot meant to be actual views of any particular semiconductor device, butare merely idealized representations which are employed to more clearlyand fully depict the formation of contact interfaces in the presentinvention than would otherwise be possible. Additionally, elementscommon between FIGS. 1-8 retain the same numerical designation.

Although the examples presented are directed to the formation of cobaltsilicide contact interfaces, any metal or metal alloy which is capableof forming a silicide may be employed, including, but not limited to,titanium, platinum, or palladium.

FIG. 1 illustrates a semiconductor substrate 100, such as asilicon-containing substrate, having a polysilicon layer 102 thereon,wherein at least one active-device region 104 is formed in a polysiliconlayer 102, with a thin dielectric layer 106, such as TEOS, of athickness of approximately 1 kA disposed over the polysilicon layer 102.A layer of barrier material 108, preferably titanium nitride depositedto a thickness of between about 100-150 Å, is deposited over the thindielectric layer 106, such as by PVD, as shown in FIG. 2. Otherpotential barrier materials include tungsten nitride, tungsten siliconnitride, titanium silicon nitride, and the like.

A mask material 112 is patterned on the barrier material layer 108, asshown in FIG. 3. A contact opening 114 is then etched through thebarrier material layer 108 and the thin dielectric layer 106, preferablyby a dry etch such as reactive ion etching or the like, to expose aportion of the active-device region 104, then any remaining maskmaterial 112 is removed, as illustrated in FIG. 4. A thin layer ofcobalt 116 is deposited, preferably by PVD, over the barrier materiallayer 108 and into the contact opening 114 over the exposed portion ofthe active-device region 104, as shown in FIG. 5. A high temperatureanneal step, preferably between about 400 and 800° C., most preferablybetween about 450 and 600° C. for between about 5 seconds and 1 hour, isconducted in an inert atmosphere, preferably nitrogen containing gas, toreact the thin cobalt layer 116 with the active-device region 104 incontact therewith which forms a cobalt silicide layer 118, as shown inFIG. 6. The barrier material layer 108 prevents the formation of cobaltsilicide structures within voids and imperfections in the thindielectric layer 106. In particular, it has been found that a thintitanium nitride film acts as a good diffusion barrier for a thin TEOSdielectric layer. Further, it has been found that titanium nitride doesnot react with cobalt. Thus, cobalt silicide patch formations have beeneliminated when titanium nitride is used as a barrier layer over a thinTEOS dielectric layer.

The nonreacted cobalt layer 116 is removed, preferably by a wet etchsuch as hydrochloric acid/peroxide or sulfuric acid/peroxide mixtures,wherein the barrier material layer 108 preferably acts as an etch stop,as shown in FIG. 7. Preferably, the nonreacted cobalt layer 116 isetched in a dilute HPM (Hydrochloric acid/Peroxide Mixture) solution(typically, 1 volume of hydrochloric acid to 1 volume of peroxide to 5volumes of water) for about 30 seconds at about 30° C. Such an HPMsolution is preferred because its selectivity is greater than 10⁴ forcobalt against cobalt silicide and titanium nitride.

As shown in FIG. 8, the remaining barrier material layer 108 is thenremoved, preferably by etching in an APM solution (Ammonia/PeroxideMixture) solution (typically, 1 volume of ammonia to 1 volume ofperoxide to 5 volumes of water) for between about 1 and 2 minutes atabout 65° C. Such an APM solution is preferred because of itsselectivity for titanium nitride against cobalt silicide and TEOS.

It is contemplated that the process of the present invention may beutilized for production of DRAM chips, wherein the contact interfacesare used in the MOS structures within a memory array of a DRAM chip.Such a MOS structure 200 is illustrated in FIG. 9 as a portion of amemory array in a DRAM chip. The MOS structure 200 comprises asemiconductor substrate 202, such as a lightly doped P-type crystalsilicon substrate, which has been oxidized to form thick field oxideareas 204 and exposed to implantation processes to form drain regions206 and source regions 208. Transistor gate members 212, including awordline 214 bounded by insulative material 216, are formed on thesurface of the semiconductor substrate 202 and thick field oxide areas204. A barrier layer 218 is disposed over the semiconductor substrate202, the thick field oxide areas 204, and the transistor gate members212. The barrier layer 218 has bitline contacts 222 contacting thesource regions 208 for electrical communication with a bitline 224 and,further, has capacitor contacts 226 contacting the drain regions 206 forelectrical communication with memory cell capacitors 228. Each of thebitline contacts 222 and capacitor contacts 226 may have silicide layerinterfaces 232, formed as described above, for reducing resistancebetween the bitline contacts 222 and the source regions 208, and betweenthe capacitor contacts 226 and the drain regions 206. The memory cellcapacitors 228 are completed by depositing a dielectric material layer234, then depositing a cell poly layer 236 over the dielectric materiallayer 234.

FIGS. 10-17 illustrate a method of forming a testing contact used inbackend testing of semiconductor devices. It should be understood thatthe illustrations are not meant to be actual views of any particularsemiconductor device, but are merely idealized representations which areemployed to more clearly and fully depict the formation of contactinterfaces in the present invention than would otherwise be possible.Additionally, elements common between FIGS. 10-17 retain the samenumerical designation.

FIG. 10 illustrates a substrate 302 having at least one contactprojection 304 disposed thereon, preferably with a height ofapproximately 100 μm, wherein the substrate 302 and the contactprojection 304 have a first dielectric layer 306, preferably silicondioxide, disposed thereover. The first dielectric layer 306 may bedeposited by any known technique or, if silicon dioxide, may be grown onthe surface of the substrate 302 by a thermal oxidation process. A layerof polysilicon 308 is deposited by any known technique over the firstdielectric layer 306. As shown in FIG. 11, a second dielectric layer312, such as TEOS or silicon dioxide, is deposited over the polysiliconlayer 308 and a layer of barrier material 314, preferably titaniumnitride, is deposited over the second dielectric layer 312, such as byPVD.

A mask material 316 is patterned on the barrier material layer 314, asshown in FIG. 12. The barrier material layer 314 and the seconddielectric layer 312 are then etched, preferably by a dry etch such asreactive ion etching or plasma etching, to expose the polysilicon layer308 over the contact projection 304, then any remaining mask material316 is removed, as illustrated in FIG. 13. A thin layer of cobalt 318 isdeposited, preferably by PVD, over the barrier material layer 314 andonto the exposed contact projection 304, as shown in FIG. 14. A hightemperature anneal step, preferably between about 400 and 800° C., mostpreferably between about 450 and 600° C. for between about 5 seconds and1 hour, is conducted in an inert atmosphere, preferably nitrogencontaining gas, to react the thin cobalt layer 318 with the exposedportion of the polysilicon layer 308 over the contact projection 304which forms a cobalt silicide layer 322, as shown in FIG. 15.

The nonreacted cobalt layer 318 is removed, preferably by a wet etch,such as hydrochloric acid/peroxide or sulfuric acid/peroxide mixtures,wherein the barrier material layer 314 preferably acts as an etch stop,as shown in FIG. 16. Preferably, the nonreacted cobalt layer 318 isetched in a dilute HPM (Hydrochloric acid/Peroxide Mixture) solution(typically, 1 volume of hydrochloric acid to 1 volume of peroxide to 5volumes of water) for about 30 seconds at about 30° C.

As shown in FIG. 17, the remaining barrier material layer 314 is thenremoved, preferably etching in an APM (Ammonia/Peroxide Mixture)solution (typically, 1 volume of ammonia to 1 volume of peroxide to 5volumes of water) for between about 1 and 2 minutes at about 65° C., andthe remaining second dielectric layer 312 and polysilicon layer 308 arealso removed, by any known technique. The cobalt silicide layer 322 isnot disturbed by the removal of the remaining barrier material layer 314or the removal of the second dielectric layer 312 and polysilicon layer308, as dry etches containing chlorine or fluorine will not etch cobaltsilicide (i.e., CoF_(x) and CoCl_(x) are nonvolatile).

Structures such as illustrated in FIG. 17 are generally used for testingof flip-chips, wherein, as illustrated in FIG. 18, solder bumps 332 of aflip-chip 330 electrically contact the cobalt silicide layer 322. Thecobalt silicide layer 322 conducts electrical signals to and/or receiveselectrical signals from the flip-chip 330 through the solder bumps 332.

FIGS. 19-26 illustrate another method of forming a testing contact usedin backend testing of semiconductor devices. Elements common betweenFIGS. 10-17 and FIGS. 19-26 retain the same numerical designation.

FIG. 19 illustrates a substrate 302 having at least one contactprojection 304 disposed thereon, wherein the substrate 302 and thecontact projection 304 have a first dielectric layer 306, preferablysilicon dioxide, disposed thereover. A layer of polysilicon 308 isdeposited by any known technique over the first dielectric layer 306. Asshown in FIG. 20, a layer of barrier material 314, preferably titaniumnitride, is deposited over the polysilicon layer 308.

A mask material 316 is patterned on the barrier material layer 314, asshown in FIG. 21. The barrier material layer 314 is then etched toexpose the polysilicon layer 308 over the contact projection 304, thenany remaining mask material 316 is removed, as illustrated in FIG. 22. Athin layer of cobalt 318 is deposited over the barrier material layer314 and onto the exposed contact projection 304, as shown in FIG. 23. Ahigh temperature anneal step, preferably between about 400 and 800° C.,most preferably between about 450 and 600° C. for between about 5seconds and 1 hour, is conducted in an inert atmosphere, preferablynitrogen containing gas, to react the thin cobalt layer 318 with theexposed portion of the polysilicon layer 308 over the contact projection304 which forms a cobalt silicide layer 322, as shown in FIG. 24.

The nonreacted cobalt layer 318 is removed, preferably by a wet etch,such as hydrochloric acid/peroxide or sulfuric acid/peroxide mixtures,wherein the barrier material layer 314 preferably acts as an etch stop,as shown in FIG. 25. As shown in FIG. 26, the remaining barrier materiallayer 314 and the remaining polysilicon 308 are removed.

Having thus described in detail preferred embodiments of the presentinvention, it is to be understood that the invention defined by theappended claims is not to be limited by particular details set forth inthe above description as many apparent variations thereof are possiblewithout departing from the spirit or scope thereof.

1. A method for forming a contact interface, comprising: forming atleast one protruding contact structure on a substrate, the at least oneprotruding contact structure being configured to be received by a recessof a contact pad of a semiconductor device component; and forming asilicide contact over at least a portion of the at least one protrudingcontact structure.
 2. The method of claim 1, wherein forming thesilicide contact comprises forming the silicide contact so as to beelectrically isolated from the substrate.
 3. The method of claim 2,further comprising: forming a layer comprising dielectric material overat least a portion of the at least one protruding contact structureprior to forming the silicide contact.
 4. The method of claim 3, whereinforming the layer comprising dielectric material comprises formingsilicon dioxide.
 5. The method of claim 3, wherein forming the layercomprising dielectric material comprises depositing TEOS.
 6. The methodof claim 3, wherein forming the at least one protruding contactstructure comprises forming the at least one protruding contactstructure from a semiconductor substrate.
 7. The method of claim 3,wherein forming the silicide contact comprises: forming a layercomprising silicon over the layer comprising dielectric material;forming a layer comprising electrically conductive silicidable materialover the layer comprising silicon; and annealing the silicon and theelectrically conductive silicidable material.
 8. The method of claim 7,wherein forming the layer comprising electrically conductive silicidablematerial comprises forming a layer comprising cobalt.
 9. The method ofclaim 7, wherein annealing is effected by heating at least the siliconto a temperature of about 400° C. to about 800° C.
 10. The method ofclaim 7, wherein annealing is effected by heating at least the siliconto a temperature of about 450° C. to about 600° C.
 11. The method ofclaim 7, further comprising: removing an unreacted portion of theelectrically conductive silicidable material.
 12. The method of claim11, wherein removing the unreacted portion is effected withoutsubstantially removing reacted electrically conductive silicidablematerial.
 13. The method of claim 11, wherein removing the unreactedportion is effected with a hydrochloric/peroxide mixture solution. 14.The method of claim 7, wherein forming the silicide contact furthercomprises: forming another layer comprising dielectric material over thelayer comprising silicon, prior to forming the layer comprisingelectrically conductive silicidable material.
 15. The method of claim14, wherein forming the another layer comprising dielectric materialcomprises depositing silicon dioxide.
 16. The method of claim 14,wherein forming the silicide contact further comprises: exposing aportion of the layer comprising silicon through the another layercomprising dielectric material.
 17. The method of claim 14, whereinforming the silicide contact further comprises: forming a layercomprising barrier material over the another layer comprising dielectricmaterial, prior to forming the layer comprising electrically conductivesilicidable material.
 18. The method of claim 17, wherein forming thelayer comprising barrier material comprises forming a layer comprisingat least one of titanium nitride, tungsten nitride, tungsten siliconnitride, and titanium silicon nitride.
 19. The method of claim 17,wherein forming the silicide contact further comprises: exposing aportion of the layer comprising silicon through the layer comprisingbarrier material and the another layer comprising dielectric material.20. The method of claim 19, wherein annealing is effected through thebarrier layer and the another layer comprising dielectric material. 21.The method of claim 20, further comprising: removing an unreactedportion of the electrically conductive silicidable material.
 22. Themethod of claim 21, wherein removing the unreacted portion is effectedwithout substantially removing the barrier material.
 23. The method ofclaim 17, wherein forming the layer comprising barrier materialcomprises preventing the electrically conductive silicidable materialfrom reacting with the silicon through at least one of a void and animperfection in the another layer comprising dielectric material. 24.The method of claim 17, further comprising: removing the layercomprising barrier material after forming the silicide contact.
 25. Themethod of claim 24, wherein removing the layer comprising barriermaterial is effected without substantially removing the silicidecontact.
 26. The method of claim 24, wherein removing the layercomprising barrier material is effected without substantially removingthe layer comprising dielectric material.
 27. The method of claim 24,wherein removing the layer comprising barrier material comprisessubstantially completely removing the barrier material.
 28. The methodof claim 24, wherein removing is effected with an ammonia/perioxidemixture solution.